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SIP12117 www.vishay.com vishay siliconix s17-0307-rev. b, 06-mar-17 1 document number: 62973 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 3 a current mode constant on-time synchronous buck regulator description the SIP12117 is a high frequency current-mode constant on-time (cm-cot) synchronous buck regulator with integrated high-side and lo w-side power mosfets. its power stage is capable of suppl ying up to 3 a continuous current at 600 khz switching frequency. this regulator produces an adjustable output voltage down to 0.6 v from 4.5 v to 15 v input rail to accommodate a variety of applications, including consumer electronics, computing, telecom, and industrial. SIP12117s cm-cot architecture delivers ultrafast transient response and low ripple over the full load range with minimum output capacitance and no esr requirements. the device features a built in soft start of 2.9 ms and integrated compensation. the device also includes cycle-by-cycle current limit, over temperature protection (otp) and input under-voltage lockout (uvlo). the SIP12117 is available in lead (pb)-free 3 mm x 3 mm dfn 10 lead package with thermal pad. features ? 4.5 v to 15 v input voltage ? adjustable output voltage down to 0.6 v ? 3 a continuous output current ? integrated compensation ? 600 khz switching frequency ? ultrafast transient response ? < 5 a typical shutdown current ? cycle by cycle current limit ? power good function ? fixed soft start: 2.9 ms, typ. ? material categorization: fo r definitions of compliance please see www.vishay.com/doc?99912 applications ? graphics cards ? set-top-box ?lcd tv ? notebook computers ? hdd / ssd ? ? typical application circiut and package options fig. 1 - typical application circuit for SIP12117 s ip12117 v in p g ood en v cc lx p g nd power good enable v out fb boot input 4.5 v to 15 v
SIP12117 www.vishay.com vishay siliconix s17-0307-rev. b, 06-mar-17 2 document number: 62973 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pin configuration fig. 2 - SIP12117 pin configuration (bottom view) ? ? marking pin configuration pin number name function 1fb feedback voltage 0.6 v (typ.) input. use a resistor divider between v out and thermal pad to set the output voltage 2v cc internal regulator output 3v in input supply voltage for power mos and regulator. v in = 4.5 v to 15 v 4, 5 p gnd power ground 6, 7 lx switching node, inductor connection point 8boot bootstrap pin - connect a capacitor of at least 100 nf from boot to lx to deve lop the floating supply for the high-side gate driver 9p good power good output. open drain 10 en enable input. pull enable above 1.5 v to enable an d below 0.4 v to disable the part. do not float this pin pad a gnd analog ground. the pad also improves thermal performance ordering information part number package marking (line 1: p/n) SIP12117dmp-t1-ge4 dfn10 3 x 3 2117 SIP12117db reference board 1 fb 2 v cc 3 v in 4 p g nd 5 p g nd lx 6 lx 7 boot 8 p g ood 9 en 10 a g nd pad format: line 1: dot line 2: p/n line 3: s iliconix logo + e s d dymbol line 4: factory code + year code + work week code + lot code p/n fywll
SIP12117 www.vishay.com vishay siliconix s17-0307-rev. b, 06-mar-17 3 document number: 62973 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 ? stresses beyond those listed under absolute maximum ratings ma y cause permanent damage to th e device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those in dicated in the operational sectio ns of the specifications is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. absolute maximum ratings electrical parameter conditions limit unit v in reference to p gnd -0.3 to +16 v v cc reference to a gnd -0.3 to +6 lx reference to p gnd -1 to +16 lx (ac) 100 ns -2 to +17 10 ns -6 to +17 boot reference to p gnd -0.3 to v in + v cc all logic input and output (en, fb, p good ) reference to a gnd -0.3 to v cc + 0.3 temperature junction temperature -40 to +150 c storage temperature -65 to +150 power dissipation junction to ambien t thermal impedance (r thja ) 36.3 c/w esd protection electronic discharge protection hbm 2 kv recommended operating range (all voltages referenced to gnd = 0 v) electrical parameter mi nimum typical maximum unit v in 4.5 - 15 v v out 0.6 - 5.5 temperature recommended ambient te mperature -40 to +85 c operating junction temperature -40 to +125
SIP12117 www.vishay.com vishay siliconix s17-0307-rev. b, 06-mar-17 4 document number: 62973 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note (1) not tested, guaranteed by design. electrical specifications (test condition unless otherwise specified) parameter symbol test condition v in = 12 v, t a = -40 c to +85 c limits unit min. typ. max. power supply input voltage v in 4.5 - 15 v v cc voltage v cc -5- input current iv in_noload t a = 25 c, non-switching, no load - 1.5 - ma shutdown current iv in_shdn en = 0 v - 5 10 a v in u vlo threshold v in_uvlo rising edge - 2.8 - v v in u vlo hysteresis v in_uvlo_hys - 550 - mv controller and timing feedback voltage v fb t a = 25 c 588 600 612 mv t a = -40 c to +85 c 585 600 615 v fb input bias current i fb - - 100 na on-time (600 khz) t on v in = 12 v, (v out = 1 v) - 138 - ns soft start timing (1) -2.95ms power mosfets high-side on resistance r on_hs v gs = 5 v - 85 140 m ? low-side on resistance r on_ls - 55 105 fault protections over current limit i ocp inductor valley current, t a = 25 c 3.6 4.25 5.1 a over temperature protection (1) rising temperature - 145 - c hysteresis - 35 - power good power good output threshold v fb_rising_vth_ov rising (% v out )-95- % v fb_falling_vth_uv falling (% v out )--10- power good pull low resistance r on_pgood -2850 ? power good delay time t dly_pgood -8-s enable threshold logic high level v en_h 1.5 - - v logic low level v en_l --0.4
SIP12117 www.vishay.com vishay siliconix s17-0307-rev. b, 06-mar-17 5 document number: 62973 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 ? functional block diagram fig. 3 - SIP12117 functi onal block diagram on-time generator + - pwm comparator s oft s tart 0.6 v reference p g ood v cc en v fb boot lx p g nd v in v cc anti-xcond control 9 2 10 control logic s ection ocp uvlo otp ota + - + i s en s e 1 i-v converter i s en s e pad current mirror 3 8 boot 6, 7 regulator zcd 4, 5
SIP12117 www.vishay.com vishay siliconix s17-0307-rev. b, 06-mar-17 6 document number: 62973 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics ? (v in = 12 v, v out = 1 v, l = 1.5 h, c = 3 x 22 f (ceramic), unless noted otherwise) fig. 4 - efficiency vs. i out fig. 5 - frequency variation vs. i out fig. 6 - load regulation vs. i out fig. 7 - steady-state, i out = 3 a time = 2 s/div fig. 8 - steady-state, i out = 0 a time = 2 s/div 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 efficiency (%) i out (a) 1 v out 5 v out 0 100 200 300 400 500 600 700 800 900 1000 0 0.5 1.0 1.5 2.0 2.5 3.0 s witching fre q uency (khz) i out (a) 1 v out 5 v out -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 load regulation (%) i out (a) 1 v out 5 v out icoil 1 a/div vout 50 mv/div lx 10 v/div icoil 1 a/div vout 50 mv/div lx 10 v/div
SIP12117 www.vishay.com vishay siliconix s17-0307-rev. b, 06-mar-17 7 document number: 62973 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 9 - load step undershoot response,i out = 0 a to 1.5 a time = 10 s/div fig. 10 - load step undershoot response, i out = 0 a to 3 a time = 10 s/div fig. 11 - start-up, i out = 0 a time = 1 s/div fig. 12 - load step overshoot response, i out = 1.5 a to 0 a time = 10 s/div fig. 13 - load step overshoot response, i out = 3 a to 0 a time = 10 s/div fig. 14 - shut-down, i out = 0 a time = 200 ms/div vout 50 mv/div icoil 2 a/div lx 10 v/div vout 100 mv/div icoil 2 a/div lx 10 v/div vout 500 mv/div icoil 1 a/div lx 10 v/div en 5 v/div vout 50 mv/div icoil 2 a/div lx 10 v/div vout 100 mv/div icoil 2 a/div lx 10 v/div en 5 v/div vout 500 mv/div icoil 1 a/div lx 10 v/div
SIP12117 www.vishay.com vishay siliconix s17-0307-rev. b, 06-mar-17 8 document number: 62973 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 15 - load step undershoot response i out = 0 a to 3 a time = 1 ms/div fig. 16 - over current protection, i valley = 4 a time = 100 s/div fig. 17 - shut-down, i out = 3 a time = 50 s/div fig. 18 - over current protection, i valley = 4 a time = 20 s/div vout 500 mv/div en 5 v/div icoil 2 a/div lx 10 v/div vout 500 mv/div icoil 2 a/div lx 10 v/div vout 500 mv/div icoil 2 a/div lx 10 v/div en 5 v/div vout 500 mv/div icoil 2 a/div lx 10 v/div
SIP12117 www.vishay.com vishay siliconix s17-0307-rev. b, 06-mar-17 9 document number: 62973 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 operational description device overview SIP12117 is a high-efficiency monolithic synchronous buck regulator capable of deli vering up to 3 a continuous current. the device has fixed switching frequency of 600 khz. the control scheme is based on current - mode constant-on-time architecture, which delivers fast transient response and minimi zes external compone nts. thanks to the internal current ramp inform ation, no high-esr output bulk or virtual esr network is required for the loop stability. SIP12117 has a full set of protection features: ? cycle by cycle over current protection ? over temperature protection with hysteresis the device also features a dedicated enable pin for easy power sequencing and an op en drain power good output. the device is available in 3 x 3 dfn10 package with an exposed power pad to deliver high power density with ease of use. power stage SIP12117 integrates a high-performance power stage with an 85 m ? n-channel high side mosfet and a 55 m ? n-channel low side mosfet. the mosfets are optimized to achieve up to 95 % efficiency at 600 khz switching frequency. the power input voltage (v in ) can go up to 15 v and down as low as 4.5 v for power conversion. pwm control mechanism SIP12117 employs a state-of-the-art current - mode cot (cm-cot) control mechanism. during steady-state operation, output voltage is compared with internal reference (0.6 v typ.) and th e amplified error signal (v comp ) is generated. in the meantime, inductor valley current is sensed, and its slope (i sense ) is converted into a voltage signal (v current ) to be compared with v comp . once v current is lower than v comp , a single shot on-time is generated for a fixed time set by an internal r on . light load operation to further improve efficiency at light-load condition, SIP12117 provides a set of innovative implementations to eliminate ls recirculating current and switching losses. the internal zero crossing detect or (zcd) monitors lx node voltage to determine when inductor current starts to flow negatively. in light load operation as soon as inductor valley current crosses zero, the de vice first deploys diode emulation mode by turning off ls fet. if load further decreases, switching freq uency is further reduced proportional to load condition to save switching losses while keeping output ripple within tolerance. the switching frequency is set by the control loop to maintain regulation. at zero load this frequency can go as low as hundreds of hz. fig. 19 illustrates the basi c block diagram for cm-cot architecture and fig. 20 demonstrates the basic operational principle: fig. 19 - cm-cot block diagram fig. 20 - cm-cot operational principle h g l g h g l g ota - + bandgap v ref v out current mirror l s fet pwm comperator - + - + v in i-amp on-time generator v in r on control logic & mo s fet driver v comp i s en s e v current v current v comp pwm fixed on-time
SIP12117 www.vishay.com vishay siliconix s17-0307-rev. b, 06-mar-17 10 document number: 62973 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 output monitoring and protection features output over-current protection (ocp) SIP12117 has cycle by cycle over-current limit control. the inductor valley current is monitored during ls fet turn-on period through r ds(on) sensing. after a pre-defined blanking time, the valley current is compared with internal threshold (4.25 a typ.) to dete rmine the threshold for ocp. if the monitored current is higher than the internal threshold, hs turn-on pulse is skipped and ls fet is kept on until the valley current returns below ocp limit. ocp is enabled immediately after v in passes uvlo level and enable is high. in the figure below we see the ri pple current riding on the dc load current. the valley current is calculated by taking one half the ripple current minus the dc load current. for example if i out = 3 a and ripple current = 1.2 a, i valley = 3 a - 0.6 a = 2.4 a. the typical dc full load current would be 4.85 a which is calculated by 4.25 a (ocp typ.) + 0.6 a. here we see changing the ripple current (inductor value) can change the maximum dc load current value. fig. 21 - over-current protection illustration negative current protection similar to the output over-cu rrent protection, the negative current protection is realized by monitoring the current across the ls fet. ? when the valley point of the in ductor current reaches -2.5 a for first cycles, both hs and ls fets are off. over-temperature protection (otp) SIP12117 has internal thermal monitor block that turns off both hs and ls fets wh en junction temperature is above 145 c (typ.). a hysteresis of 35 c is implemented, so when junction temperatu re drops below 110 c, the device restarts by initiating soft-start sequence again. soft start SIP12117 has a built in soft-start function of ~2.9 ms. once v in is above uvlo level (2.8 v typ.), v out will ramp up slowly, rising monotonically to the programmed output voltage. pre-bias startup in case of pre-bias startup, th e output is monitored through the fb pin. if the sensed voltage on fb is higher than the internal reference ra mp value, control l ogic prevents hs and ls fet from switching to avoid a negative output voltage spike due to ls fet turn on. ? ? design procedure the design process of the SIP12117 is quite straight forward. only few passive components such as output capacitors and inductor need to be selected. the following paragraph desc ribes the selection procedure for these peripheral components for a given operating conditions. in the next example the following definitions apply: v in max.: the highest specified input voltage v in min.: the minimum effectiv e input voltage subject to voltage drops due to connectors, fuses, switches, and pcb traces. there are two values of load current to evaluate - continuous load current and peak load current. continuous load current relates to thermal stress considerations which drive the selection of the inductor and input capacitors. peak load current determine s instantaneous component stresses and filtering requirements such as inductor saturation, output capacitors, an d design of the current limit circuit. the following specifications are used in this design: ?v in = 12 v 10 % ?v out = 1.2 v 1 % i load ocp thre s hold i inductor g h s kipped g h pul s e
SIP12117 www.vishay.com vishay siliconix s17-0307-rev. b, 06-mar-17 11 document number: 62973 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 inductor selection in order to determine the indu ctance, the ripple current must first be defined. cost, pcb size , output ripple, and efficiency are all used in the selection process. low inductor values result in smaller size and allo w faster transient performance but create higher ripple current which can reduce efficiency. higher inductor values will reduce the ripple current, and transient response. efficiency especially at higher load currents will also be compromi sed due to the higher dcr (within a give n case size). the ripple current also sets the boundary for power-save operation. the switching regu lator will typically enter power-save mode when the load current decreases to 1/2 of the ripple current. for example, if ripple current is 1 a then power-save operation will typically start at loads approaching 0.5 a. alternatively, if ripple current is set at 40 % of maximum load current, then power-save will start for loads less than ~ 20 % of maximum current. setting the ripple current 20 % to 50 % of the maximum load current provides an optimal trad e-off of the areas mentioned above. this table provides a simple ea sy guide for setting up the board. if excessive jitter is noticed then reducing the inductor to the next standard value may be needed. ? the equation for determining inductance is shown next. example in this example, the inductor ripple current is set equal to 30 % of the maximum load curre nt. thus ripple current will be 30 % x 3 a or 0.9 a. to find the minimum inductance needed, use the v in and t on values that correspond to v in max. . plugging numbers into th e above equation we get ? ? a smaller value of 1.5 h is selected which is a standard value. this will increase the maximum ripple current by 25 %. note that the inductor must be rated for the maximum dc load current plus 1/2 of the ripple current. the actual ripple current using the chosen 1 h inductor comes out to be. output capacitance calculation the output capacitance is usually chosen to meet transient requirements. a worst-case lo ad release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capacitance. if the load release is instantaneou s (load changes from maximum to zero in < 1/f sw s), the output capacitor must absorb all the inductor's stored energy. this will approximately cause a peak voltage on the capacitor according to the following equation. assuming a peak voltage v peak of 1.3 v (100 mv rise upon load release), and a 3 a load release, the required capacitance is shown by the next equation. if the load release is relatively slow, the output capacitance can be reduced. using mlcc ceramic capacitors we will use 3 x 22 f or 66 f as the total output capacitance. switching frequency variations the switching frequency variat ion in cot can be mainly attributed to the increase in conduction losses as the load increases. since the on time is constant the controller must account for losses and maintain output regulation by reducing the off time. hence the f sw tends to increase with load. SIP12117 configuration look up table v in (v) v out (v) inductor (h) r fb_top ( ? ) r fb_bottom ( ? ) 12 1 1.5 4.53k 6.81k 12 3.3 3.3 4.53k 1k 12 5 3.3 4.53k 619r 5 1 1.5 4.53k 6.81k 5 3.3 1.5 4.53k 1k l = (v in - v out ) x t on i l = (13.2 v - 1.2 v) x = 2 h 151 x 10 -9 s 0.9 a i = (13.2 v - 1.2 v) x = 1.2 a 151 n s 1.5 h c out min. = 1 2 l x (i out +x i ripple max. ) 2 (v peak ) 2 - (v out ) 2 c out min. = = 77.8 f 1.5 h x (3 a + 0.5 x (1.2 a) 2 (1.3 v) 2 - (1.2 v) 2
SIP12117 www.vishay.com vishay siliconix s17-0307-rev. b, 06-mar-17 12 document number: 62973 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 layout considerations the SIP12117 offers the desi gner a small part count, 3 a buck regulator solution. if the below layout recommendations are followed, the same layout can be used to cover a wide range of output currents and voltages without any changes to the board design and only minor changes to the component values in the schematic. the reference design has a majority of the components placed on the top layer. this allows for easy assembly and straightforward layout. fig. 22 outlines the pointers for the layout considerations and the explanations follow. fig. 22 - reference design pointers 1. place input ceramic capacitors close to the voltage input pins with a small 10 nf / 100 nf placed as close as the design rules will allow. this will help reduce the size of the input high frequency current loop and consequently reduce the high frequency ripple noise seen at the input and the lx node. 2. place the setup and control passive devices logically around the ic with the intention of placing a quiet ground plane beneath them on a secondary layer. 3. it is advisable to use ceramic capacitors at the output to reduce impedance. place these as close to the ic p gnd and output voltage node as design will allow. place a small 10 nf / 100 nf ceramic capacitor closest to the ic and inductor loop. 4. the loop between lx, v out and the ic p gnd should be as compact as possible. this will lower series resistance and also make the current l oop smaller enabling the high frequency response of the ou tput capacitors to take effect. 5. the output impedance should be small when high current is required; use high current traces, multiple layers can be used with many vias if the design allows. 6. use many vias when multiple layers are involved. this will have the effect of lowering the resistance between layers and reducing the via inductance of the pcb nets. 7. the quiet a gnd should be connected to the p gnd plane near to the input gnd at one connection only of at least 1 mm width. 8. p gnd can be used on internal layers if the resistance of the pcb is to be small; this will also help remove heat. use extra vias if needed but be mindful to allow a path between the vias. 9. a quiet plane should be employed for the a gnd , this is placed under the small signal passives. this can be placed on multiple layers if needed for heat removal. 10. the lx copper can also be used on a single or multiple layers, use a number of vias to stitch the layers. 11. the copper area beneath the inductor has been removed (on all layers) in this desi gn to reduce the inductive coupling that occurs between the inductor and the gnd trace. no other voltage plan es should be placed under this area. v out 0v v in 1 3 2 4 5 8 10 lx 5 6 11 7 9
SIP12117 www.vishay.com vishay siliconix s17-0307-rev. b, 06-mar-17 13 document number: 62973 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pcb layout fig. 23 - top layer fig. 24 - inner layer 2 fig. 25 - inner layer 1 fig. 26 - bottom layer
SIP12117 www.vishay.com vishay siliconix s17-0307-rev. b, 06-mar-17 14 document number: 62973 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 schematic bill of material (v in = 12 v, v out = 3.3 v, f sw = 600 khz) item qty reference pcb footprint value voltage part number manufacturer 1 2 c1, c2 1210 10 f 35 v c1210c106m6pactu kemet 2 2 c3, c6 0402 10 nf 50 v grm155r71h103ka88d murata 3 1 c4 0603 1 f 10 v c0402c105m8pactu kemet 4 1 c5 0402 100 nf 35 v cga2b3x7r1v104k050bb vishay 5 2 c7, c8 0805 22 f 10 v cl21a226mpqnnne samsung 6 1 r2 0402 20r - crcw040220r0fked vishay 7 1 r3 0402 4k53 - crcw04024k53fked vishay 8 1 r4 0402 1k - crcw0402249kfked vishay 9 1 l1 ihlp2525 33 - ihlp2020bzer3r3m01 vishay 10 1 u1 dfn10-3x3 - - SIP12117 vishay 11 1 r1 0402 4k53 - crcw04024k53fked vishay 12 1 r5 0402 1k - crcw0402249kfked vishay 13 1 r6 0402 10k - crcw040210k0fked vishay 14 4 p3, p4, p5, p6 hdr1x2 - - 90120-0126 vishay 15 2 p1, p2 term2 - - 282834-2 te connectivity 1 2 p3 header 2 1 2 p1 terminal 1 2 p4 header 2 1 2 p2 terminal 1 2 p5 header 2 1 2 p6 header 2 v in en p g d v cc boot lx lx vfb g nd g nd g nd header 2 0 v 0 v 0 v r4 1 k r6 10 k r3 4.53 k r1 4.53 k r5 1 k r2 20 0 v u1 s ip12117 3 2 8 b s b s 1 v in en 10 p g d9 5 v c4 1 f p1 5 4 6 1 7 vfb lx 3.3 h c9 omit c6 c7 c8 10 nf 22 f 22 f v out c1 c2 c3 10 nf 10 f 10 f l1 100 nf c5
SIP12117 www.vishay.com vishay siliconix s17-0307-rev. b, 06-mar-17 15 document number: 62973 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 case outline notes (2) use millimeters as the primary measurement. (3) n is the number of terminals. (4) dimensions b applies to me talized terminal and is measured betwee n 0.15 mm and 0.30 mm from terminal tip. (5) coplanarity applies to the exposed heat sink slug as well as the terminal. (6) the pin #1 identifier may be either a mold or marked feature, it must be located within the zone indicated. dimension millimeters (1) inches min. nom. max. min. nom. max. a 0.80 0.90 1.00 0.031 0.035 0.039 a1 0 0.02 0.05 0 0.001 0.002 a3 0.20 bsc 0.008 bsc b 0.18 0.23 0.30 0.007 0.009 0.012 d 3.00 bsc 0.118 bsc d2 2.20 2.38 2.48 0.087 0.094 0.098 e 0.50 bsc 0.020 bsc e 3.00 bsc 0.118 bsc e2 1.49 1.64 1.74 0.059 0.065 0.069 l 0.30 0.40 0.50 0.012 0.016 0.020 bottom view e d d/2 e/2 s eating plane a3 a1 a s ide view c 0.08 c 0.10 // nx (3) terminal tip e c 0.10 m a b nxb e2 expo s ed pad nxl d2 index area d/2 x e/2 (5) index area d/2 x e/2 c 0.15 2 x c 0.15 2 x (3) (4) (5) top view
SIP12117 www.vishay.com vishay siliconix s17-0307-rev. b, 06-mar-17 16 document number: 62973 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 recommended land pattern ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?69273 . recommended land pattern recommended land pattern v s . ca s e outline dimen s ion s are in millimeter s 0.300 0.500 2.400 2.100 0.600 1.700 3.300
bottom view notes: 1. all dimensions are in millimeters and inches. 2. n is the total number of terminals. 3. dimension b applies to metallized terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed heat sink slug as well as the terminal. 5. the pin #1 identifier may be either a mold or marked feature, it must be located within the zone iindicated. e/2 5 index area d/2 e/2 5 c 0.15 2x c 0.15 2x package information vishay siliconix document number: 73181 29-nov-04 www.vishay.com 1 dfn-10 lead (3 x 3) millimeters inches dim min nom max min nom max a 0.80 0.90 1.00 0.031 0.035 0.039 a1 0.00 0.02 0.05 0.000 0.001 0.002 a3 0.20 bsc 0.008 bsc b 0.18 0.23 0.30 0.007 0.009 0.012 d 3.00 bsc 0.118 bsc d2 2.20 2.38 2.48 0.087 0.094 0.098 e 3.00 bsc 0.118 bsc e2 1.49 1.64 1.74 0.059 0.065 0.069 e 0.50 bsc 0.020 bsc l 0.30 0.40 0.50 0.012 0.016 0.020 *use millimeters as the primary measurement. ecn: s-42134?rev. a, 29-nov-04 dwg: 5943
legal disclaimer notice www.vishay.com vishay revision: 08-feb-17 1 document number: 91000 disclaimer ? all product, product specifications and data ar e subject to change with out notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of th e products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product , (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all implied warranties, includ ing warranties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain types of applicatio ns are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular applic ation. it is the customers responsibility to validate tha t a particular product with the prope rties described in the product sp ecification is suitable for use in a particular application. parameters provided in datasheets and / or specifications may vary in different ap plications and perfor mance may vary over time. all operating parameters, including ty pical parameters, must be va lidated for each customer application by the customer s technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product could result in personal injury or death. customers using or selling vishay product s not expressly indicated for use in such applications do so at their own risk. please contact authorized vishay personnel to obtain writ ten terms and conditions rega rding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners. ? 2017 vishay intertechnology, inc. all rights reserved

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